Array Substrate For Display Panel And Method For Manufacturing Thereof

ABSTRACT

Disclosed are an array substrate and a method of fabricating the same. The array substrate includes an active area including a plurality of pixels defined at an intersection area of a gate line and a data line, a gate driving circuit formed at one side of a non-active area and a signal line extending in parallel with the data line in the non-active area to transfer a signal to the gate driving circuit. The signal line includes a first line with a plurality of segmental lines, and at least one additional line formed of a different material and formed at a different layer than the first line. The at least one additional line electrically connects two segmental lines of the first line adjacent to each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2013-0134984, filed on Nov. 7, 2013, which is hereby incorporated byreference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to an array substrate for a display paneland a method for manufacturing thereof. More specifically, the presentdisclosure relates to a structure and a method capable of preventing adamage of a substrate due to static electricity in a display panel witha gate-in-panel (GIP) structure.

2. Description of the Prior Art

As information oriented society has been developed, demands for displaysfor displaying an image are increasing. Thus, various flat displays suchas a liquid crystal display (LCD), a plasma display panel (PDP), andorganic light, emitting display (OLED) have been used recently.

Active matrix type liquid crystal displays among the liquid crystaldisplay including an array substrate including a thin film transistor(TFT) as a switching device for controlling an on/off state of voltagefor each pixel have been generally used.

Such active matrix type liquid crystal display includes a liquid crystalpanel including the array substrate including a thin film transistor(TFT) as a switching device for controlling an on/off state of voltagefor each pixel and a color filter substrate including a color filter,and a liquid crystal layer interposed between the array substrate andthe color filter substrate. The liquid crystal display furtherimplements a driver having a driving circuit to drive the liquid crystalpanel.

The driver is generally embodied on a driving printed-circuit-board(PCB). The driving PCB can be divided into a gate driving PCB connectedto gate lines on the liquid crystal panel, and a data driving PCBconnected to data lines of the liquid crystal panel.

Also, the gate driving PCB is connected to a gate pad portion (i) formedin an edge of the liquid crystal panel and (ii) connected to the gatelines. The data driving PCB is connected to a data pad portion (i)formed in another edge of the liquid crystal panel perpendicular to theedge with the gate pad portion and (ii) connected to the data lines.Such gate and data driving PCBs are mounted on the liquid crystal panelby using, for example, a tape carrier package (TCP) or a FlexiblePrinted Circuit (FPC).

However, the driving PCB, which is divided into the gate and datadriving PCBs and loaded on the gate and data pad portions, causes thesize and weight of the liquid crystal display to increase.

To address this matter, the liquid crystal display with a gate-in-panel(GIP) structure has been proposed which allows only one driving PCB tobe loaded on one edge of the liquid crystal panel with the gate drivingcircuit directly formed on the liquid crystal panel.

FIG. 1 is a circuitry diagram schematically showing an array substrateincluded in a liquid crystal display with a GIP structure according tothe related art.

As shown in FIG. 1, the array substrate of the liquid crystal displaywith the GIP structure is divided into an active area AA used to displayimages and a non-active area NA configured to surround the active areaAA.

The active area AA includes gate line GL and data line DL configured tocross each other and to define pixel regions P, thin film transistorsTR, each connected to the respective gate line GL and data line DL, andpixel electrodes PXL connected to the respective thin film transistorsTR.

On the other hand, a part of the non-active area adjacent to a top edgeof the active area AA includes a plurality of circuit films (not shown)divisionally loaded with a data driver (not shown). Another part of thenon-active area adjacent to one of both side edges of the active area AAincludes a gate driving circuit GCA and a signal input portion SIApositioned adjacent to an edge of the gate driving circuit GCA.

The gate driving circuit GCA is configured with a plurality of circuitblocks CB1 and CB2, and each of the plurality of circuit blocks CB1 andCB2 includes a plurality of switching elements, capacitors, and so on.One circuit block CB1 of the circuit blocks is connected to the gatelines formed in the active area AA and many kinds of signal lines CL1 toCL4 formed in the signal input portion SIA.

In this specification, a line extending from the data driving circuit ordriver over the entire panel in parallel with the data lines andtransferring various signals to the gate driving circuit GCA may bereferred to as a signal input area (SIA). The line(s) included in thesignal input area SIA may be referred to as a signal line(s).

A connecting line to connect between the signal line included in suchsignal input area SIA and the circuit block of the gate driving circuitGCA may be generally referred to as a gate link line (GLL).

The signal line included in such signal input area SIA may be a metalline patterned by the gate metal layer extending from the data drivingcircuit or driver to a top of the panel, namely over the entire panel.Meanwhile, static electricity may be generated in manufacturing thesignal lines of a gate metal pattern due to friction or contacts betweenthe manufacturing device and the panel and the like, and a large amountelectric charge may be kept or charged at the gate metal pattern of suchsignal lines. During the next processes for forming the source/drainmetal layer and so on, the electrical charge maintained at the signalline pattern may be transferred over to the source/drain metal layer.

As a result, the static electricity generated in manufacturing processof patterning the signal lines and gate metal layer may destroy aninsulating layer such as a gate insulating layer between the gate metallayer and source/drain metal layer so that a gate metal layer and asource/drain metal layer may be short-circuited.

That is, during manufacturing the display panel with the GIP structure,specific signal line of the GIP is formed of a metal such as the gatemetal pattern and longitudinally extends over the entire panel so thatthe quantity of the electric charge stored on such signal line maybecome too large. Therefore, the static electricity generated inmanufacturing process of the signal line may damage a part of thedisplay panel during the following manufacturing processes.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above-mentionedproblems in the conventional art, and an aspect of the present inventionis to provide a display panel and a display device with a GIP structurethat is adapted to prevent the generation of static electricity, and amanufacturing method thereof.

Another object of the present disclosure is to provide a display paneland a display device with a GIP structure that is adapted to prevent thegeneration of static electricity on an electrical line such as a signalline and the like elongated from an active area of a display device witha GIP structure, and a manufacturing method thereof.

In accordance with an aspect of the present invention, an arraysubstrate is provided. The array substrate includes: an active areaincluding a plurality of pixels defined at an intersection area of agate line and a data line, a gate driving circuit formed at one side ofa non-active area and a signal line extending in parallel with the dataline in the non-active area to transfer a signal to the gate drivingcircuit, the signal line including a first line with a plurality ofsegmental lines, and at least one additional line formed of differentmaterial and formed at a different layer than the first line, the atleast one additional line electrically connecting two segmental lines ofthe first line adjacent to each other.

In one or more embodiments, the at least one additional line comprises asecond line, wherein the first line is formed of a gate metal and thesecond line is formed of a source/drain metal, and the second line isconnected with the first line via a contact hole formed through a gateinsulating layer.

In one or more embodiments, the at least one additional line comprises asecond line wherein the first line is formed of a gate metal and thesecond line is formed of a pixel electrode material, and the second lineis connected with the first line via a contact hole formed through agate insulating layer and a passivation layer.

In one or more embodiments, the at least one additional line comprises athird line formed of a different layer than the first line and partiallyoverlapped with two segmental lines of the first line adjacent to eachother, and a fourth line electrically connecting the two segmental linesof the first line to the third line.

In one or more embodiments, the first line is formed of a gate metal andthe third line is formed of a source/drain metal, the fourth line isformed of a pixel electrode material, the fourth line is connected toboth the first line and the third line via a contact hole formed througha gate insulating layer and passivation layer to expose a part of thefirst line and an additional contact hole formed through the passivationlayer to expose a part of the third line.

In one or more embodiments, the signal line is a forward start signalline or a backward start signal line supplying a start pulse to the gatedriving circuit and disposed between the gate driving circuit and theactive area.

In accordance with another aspect of the present invention, an arraysubstrate is provided. The array substrate includes: an active areaincluding a plurality of pixels defined at an intersection area of agate line and a data line, a gate driving circuit formed at one side ofa non-active area and a signal line extending in parallel with the dataline in the non-active area to transfer a signal to the gate drivingcircuit, wherein the signal line comprises a first line with a pluralityof segmental lines and a first additional line formed of a differentlayer than the first line and partially overlapped with two segmentallines of the first line adjacent to each other, and a second additionalline electrically connecting the two segmental lines of the first lineto the first additional line.

In accordance with another aspect of the present invention, a method offabricating an array substrate is provided. The method includes: forminga first line with a plurality of segmental lines as a part of a signalline in a non-active area by patterning a first metal layer on asubstrate, forming one or more insulating layers on the substrate onwhich a gate is patterned, forming at least one contact hole through theone or more insulating layers to expose a part of the first line andforming at least one additional line by patterning a second metal layerdifferent from the first metal layer to electrically connect twosegmental lines of the first line adjacent to each other.

In one or more embodiments, the first metal layer is a gate metal layer,the one or more insulating layers include a gate insulating layer andthe second metal layer is a source/drain metal layer.

In one or more embodiments, the first metal layer is a gate metal layer,the one or more insulating layers include a gate insulating layer and apassivation layer, and the second metal layer is a pixel electrodelayer.

In one or more embodiments, the first metal layer is a gate metal layer,the one or more insulating layers include a gate insulating layer and atleast one passivation layer, wherein forming the one or more insulationlayers, the at least one contact hole and the at least one additionalline includes: forming (i) the gate insulating layer on the substrate onwhich the gate is patterned, and (ii) a third line with a source/drainmetal, wherein ends of the third line are partially overlapped with thetwo segmental lines of the first line adjacent to each other; forming(i) the passivation layer on the non-active area, (ii) a contact holepenetrating the gate insulating layer and the passivation layer toexpose a part of the first line, and (iii) an additional contact holepenetrating the passivation layer to expose a part of the third line;and forming a fourth line electrically connecting the two segmentallines adjacent to each other to the third line through (i) the contacthole penetrating the gate insulating layer and the passivation layer,and (ii) the additional contact hole penetrating the passivation layerduring a pixel electrode patterning process.

In one or more embodiments, the signal line is a forward start signalline or a backward start signal line supplying a start pulse to the gatedriving circuit and disposed between the gate driving circuit and anactive area.

In accordance with still another aspect of the present invention, amethod of fabricating an array substrate is provided. The methodincludes forming a first line with a plurality of segmental lines as apart of a signal line in a non-active area by patterning a first metallayer on a substrate, forming one or more insulating layers on thesubstrate on which a gate is patterned, and a first additional line witha source/drain metal, wherein ends of the first additional line arepartially overlapped with two segmental lines of the first line adjacentto each other, forming a passivation layer on the non-active area, acontact hole penetrating the gate insulating layer and the passivationlayer to expose a part of the first line and an additional contact holepenetrating the passivation layer to expose a part of the firstadditional line and forming a second additional line electricallyconnecting the two segmental lines adjacent to each other to the firstadditional line through the contact hole penetrating the gate insulatinglayer and the passivation layer and the additional contact holepenetrating the passivation layer.

As mentioned above, various embodiments may prevent the generation ofstatic electricity in a display device with a GIP structure.

As mentioned above, various embodiments may prevent the generation ofstatic electricity from the elongated signal line during manufacturingthe display panel with the GIP structure, thereby preventing destroyingthe gate metal and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuitry diagram schematically showing an array substrateincluded in a liquid crystal display with a GIP structure according tothe related art;

FIG. 2 is a block diagram schematically showing an array substrateincluded in an LCD device with a GIP structure according to variousembodiments of the present disclosure;

FIG. 3 illustrates the generation of static electricity in a displaypanel to which various embodiments may be applied;

FIG. 4 is a top plan view of a part of a signal line on an arraysubstrate according to a first embodiment;

FIG. 5 is a cross-sectional view of a part of a signal line on an arraysubstrate according to a first embodiment;

FIGS. 6A through 6C are cross-sectional views showing manufacturingprocesses of the array substrate according to the first embodiment;

FIG. 7 is a cross-sectional view of a part of a signal line on an arraysubstrate according to a second embodiment;

FIGS. 8A to 8D are cross-sectional views showing manufacturing processesof the array substrate according to the second embodiment;

FIG. 9 is a top plan view of a part of a signal line on an arraysubstrate according to a third embodiment;

FIG. 10 is a cross-sectional view of a part of a signal line on an arraysubstrate according to a third embodiment; and

FIGS. 11A through 11D are cross-sectional views showing a manufacturingprocess of the array substrate according to the third embodiment.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENT

Hereinafter, a few embodiments of the present invention will bedescribed with reference to the accompanying drawings. In the followingdescription, the same elements will be designated by the same referencenumerals although they are shown in different drawings. Further, in thefollowing description of the present invention, a detailed descriptionof known functions and configurations incorporated herein will beomitted when it may not be required for the understanding of the subjectmatter of the present invention.

In addition, terms, such as first, second, A, B, (a), (b) or the likemay be used herein when describing components of the present invention.These terms are merely used to distinguish one structural element fromother structural elements, and a property, an order, a sequence and thelike of a corresponding structural element are not limited by the term.It should be noted that if it is described in the specification that onecomponent is “connected,” “coupled” or “joined” to another component, athird component may be “connected,” “coupled,” and “joined” between thefirst and second components, although the first component may bedirectly connected, coupled or joined to the second component. Likewise,when it is described, that a certain element is formed “on” or “under”another element, it should be understood that the certain element may beformed either directly or indirectly via still another element on orunder the other element. Furthermore, it should be understood that,unless otherwise indicated, elements, features or components describedherein below in connection with one of the embodiments may not belimited to this embodiment but may also be applied in the otherembodiments to form new embodiments.

Various embodiments will be described, below with reference to theaccompanying drawings.

FIG. 2 is a block diagram schematically showing an array substrateincluded in an LCD device with a GIP structure according to variousembodiments of the present disclosure.

As shown in FIG. 2, the array substrate of the LCD device with the GIPstructure according to various embodiments of the present disclosure isdivided into an active area AA used to display images and a non-activearea NA configured to surround the active area AA. A top edge of thenon-active area NA includes a pad part PA. A side edge of the non-activearea NA includes a gate driving circuit GCA and a signal input portionsSIA1 and SIA2. In one aspect, the signal input portion SIA1 ispositioned on a side edge of the gate driving circuit GCA, and thesignal input, portion SIA2 is positioned on the other side edge of thegate driving circuit GCA facing away from the side edge.

The active area AA includes gate line 110 and data line 120 configuredto cross each other and to define pixel regions P, thin film transistorsSTr each connected to the respective gate line 110 and data line 120,and pixel electrodes 130 connected to the respective thin filmtransistors STr. The thin film transistors STr are used as switchingelements.

Also, the pad part PA on the non-active area NA adjacent to a top edgeof the active area AA includes a data pad portion DP, which is connectedto the data lines 120 formed in the active area AA to connect anexternal driving printed circuit board (not shown), and a gate padportion GP, which consists of the farthest end of a plurality of signallines 140 and 140′ formed in the signal input portions SIA1 and SIA2.

The gate driving circuit. GCA is configured with a plurality of circuitblocks CB each including a plurality of driving transistors DTr,capacitors, and so on. Each of the circuit blocks CB is connected to thegate lines 110 formed on the active area AA and a plurality of gate linklines GLL extended from signal lines 140 and 140′ of the signal inputportion SIA1 and SIA2.

The signal lines 140 and 140′ defined in one embodiment may be metallines elongated from the data pad portion DP connected to the datadriving circuit to a top portion of the display panel, and supply manykinds of signals to the circuit, blocks CB of the gate driving circuitGCA.

Such signal lines 140 and 140′ may include a line VDD for supplying ahigh level driving voltage, a line VSS for supplying low level drivingvoltage, a line CLK for supplying a clock signal and a line forsupplying a start pulse (VST).

Such signal lines may be generally formed by linearly extending over theentire length of the panel, for example the entire length of the panelin FIG. 2, with the Same material and the same process as the gate metallayer.

After a gate insulating layer is formed on the gate metal layer, asemiconductor layer (active layer), a source/drain metal layer and apixel layer are sequentially formed in order to form a driving thin filmtransistor DTr in the non-active area and a switching thin filmtransistor STr in the active area. A plurality of patterning processessuch as a deposition, a lithography and an etching process may beperformed in order to form each layer, and static electricity may begenerated from an equipment used for these processes.

As mentioned above, the linear signal line extended over the entirelength of the panel is long and includes a large sectional-area, andthereby has a large quantity of electric charge. Therefore, the staticelectricity generated from the patterning process flows through thesignal line with the large quantity of electric charge so that it canfrequently induce either the damage of the gate insulating layer and thelike or the additional damage of other metal patterns such as thesource/drain metal layer by conducting over the gate insulating layer.

As shown in FIG. 2, while the signal lines 140 such as the VDD line, theVSS line, the CLK line and the like may be disposed in the signal linearea SIA1 on the outer side of the gate driving circuit GCA, namely thesignal line area farther than the gate driving circuit from the activearea, the signal lines 140′ supplying the start signal or start pulsemay be disposed in the signal line area SIA2 on the inner side of thegate driving circuit GCA, namely the signal line area between the gatedriving circuit GCA and the active area AA.

When the static electricity is generated during the patterning processof the thin film transistor in the active area or the gate drivingcircuit area, a larger amount of static electricity is conducted to thesignal lines 140 disposed between the gate driving circuit GCA and theactive area AA so that it may be more likely that damage is caused to apart of the gate driving circuit GCA and the active area AA adjacent tothe signal lines 140′ than to a part that is adjacent to other signallines, for example signal lines 140 disposed at the outer side of thegate driving circuit GCA.

The signal lines 140′ for supplying a at art pulse may include a forwardstart signal line FWst and a backward start signal line BWst forbi-directional driving or scanning. The present specificationcollectively refers to a forward start signal line FWst and a backwardstart signal line BWst as a start signal line.

FIG. 3 illustrates the generation of static electricity in a displaypanel to which various embodiments may be applied.

As shown in FIG. 3, the gate metal layer is patterned on a transparentinsulation substrate 205 such as a glass substrate. During this process,the start signal lines FWst, BWst in the signal line area SIA2 areformed on the entire panel in the longitudinal direction of the panel,namely the direction to which the data line is extended.

Subsequently, the patterning process for the thin film transistor STr inthe active area AA or the thin film transistor DTr in the gate drivingcircuit area GCA is performed, and during this patterning process, thelarge static electricity may be conducted to the start signal lines FWstand BWst having large quantity of electric charge so that it can be morelikely that damage is caused to a plurality of layers or elements of thedisplay panel such as the gate insulation layer and so on. In FIGS. 3,210 and 220 are the gate electrodes of the driving transistor DTr andthe switching thin film transistor STr respectively, and 230 is aninsulation layer.

To address this matter, in accordance with various embodiments an arraysubstrate for the display panel is proposed which includes an activearea including a plurality of pixels defined at an intersection area ofa gate line and a data line, a gate driving circuit formed at one sideof a non-active area and a signal line extending in parallel with thedata line in the non-active area to transfer a signal to the gatedriving circuit. The signal line may include a first line with aplurality of segmental lines, and at least one second line, as aconnecting line, formed of a different material and formed at adifferent layer than the first line. The second line may electricallyconnect two segmental lines of the first line adjacent to each other.

That is, one of the signal lines to which the static electricity may belargely charged is segmented into a plurality of segmental lines, e.g.gate metal lines, namely the first line with a plurality of segmentallines, and the segmental lines are connected to each other by theconnecting line at the different layer therefrom as a jumper, therebypreventing the damage from the charged static electricity generated invarious patterning processes after the gate patterning.

In an array substrate according to the first embodiment referring toFIGS. 4, 5 and 6A through 6C, among three embodiments described in thepresent specification the first line formed as a plurality of segmentallines may be formed of a gate metal and the second line may be formed ofa source/drain metal, and the second line may be connected to the firstline via a first contact hole formed through a gate insulating layer.

In an array substrate according to the second embodiment referring toFIGS. 7 and 8A through 8D, the first line may be formed of a gate metaland the second line may be formed of a pixel electrode material, and thesecond line may be connected to the first line via a second contact holeformed through a gate insulating layer and a passivation layer.

In an array substrate according to the third embodiment referring toFIGS. 9 and 10A through 10D, the second line may include a third lineformed of the different layer from the first line and partiallyoverlapped with two segmental lines of the first line adjacent to eachother, and a fourth line electrically connecting the two segmental linesof the first line to the third line.

Meanwhile, although the signal line to which each of various embodimentsis applied may be the start signal line disposed between the gatedriving circuit and the active area, embodiments of the presentdisclosure are not limited thereto, but may be applied to at least oneof all signal lines elongated for transferring a signal to a drivingcircuit on an array substrate with GIP structure, for example the VDDline, the VSS line, the CLK line and the like.

Hereafter, each of three embodiments will be described in detail inreference with the accompanying drawings.

FIGS. 4, 5 and 6A through 6C illustrate the configuration of the firstembodiment. FIG. 4 is a top plan view of a part of a signal line on thearray substrate according to the first embodiment. FIG. 5 is across-sectional view of a part of a signal line on the array substrateaccording to the first embodiment. FIGS. 6A through 6C arecross-sectional views showing manufacturing processes of the arraysubstrate according to the first embodiment.

The first embodiment relates to the signal line, specificallyforward/backward start signal line, extending in parallel with the dataline in the non-active area to transfer a signal to the gate drivingcircuit. As shown in FIG. 4, such signal line may include a first line410 with a plurality of segmental lines and a second line 420 as aconnecting line. The first line 410 is formed of the gate metal layerand is segmented into a plurality of segmental lines extending in thelongitudinal direction of the panel or the array substrate in order tobe disconnected from each other (in other words, a gap may be formed ineach case between two neighboring segmental lines). The second line 420may be formed of a source/drain metal at the different layer from thefirst line 410 and electrically connect ends of two segmental lines ofthe first line 410 adjacent to each other.

The first line 410 and the second line 420 may be connected to eachother via a first contact hole 430 which is formed through the gateinsulating layer on the top portion of the first line 410 to expose apart of the first line 410.

The total number of the segmental lines of the first line 410 extendedover the entire panel in the longitudinal direction of the panel, namelythe direction of the data lines, may be from at least two to dozens, butit is net limited thereto.

FIG. 5 illustrates a cross-sectional view of a part of a signal linetaken along I-I′ line on the array substrate on a left side, and a thinfilm transistor on a right side, according to the first embodiment.

As shown in left side of the cross-sectional view taken along I-I′ linein FIG. 5, the signal line according to the first embodiment may includethe first line 410 with a plurality of segmental lines, the firstcontact hole 430 and the second line 420. The first line 410 with theplurality of segmental lines is formed of the same metal and process asthe gate electrode 512 of the thin film transistor. The first contacthole 430 is formed through the gate insulating layer 514 on the topportion of the first line 410 to expose a part of the first line 410.The second line may be formed of the same metal and process as thesource/drain electrode 520 of the thin film transistor and electricallyconnect two segmental lines of the first line adjacent to each other viathe first contact hole 430.

Each layer of the thin film transistor shown in the right side of FIG. 5is illustrated to understand the material and the process for formingthe signal line according to the embodiment. In FIGS. 5, 522, 524 and526 indicate respectively a passivation a contact hole for a pixelelectrode and the pixel electrode.

A manufacturing method of this array substrate and the configuration ofeach layer such as the material and the process of the thin filmtransistor is explained with reference to FIGS. 6A to 6C.

FIGS. 6A to 6C are cross-sectional views showing a manufacturing processof the array substrate according to the first embodiment.

Referring to FIG. 6A, a first metal layer is formed on a transparentinsulation substrate such as a glass or a plastic substrate bydepositing a metallic material or a metal alloy for the gate ofrelatively low specific resistance such as one or more of Al, AlNd, Cu,Mo, MoTi and the like on the entire surface of the substrate andpatterning by mask and lithography processes including coating aphotoresist, exposing the photoresist to light, developing the exposedphotoresist, etching a part of the first metal layer, stripping thephotoresist and the like. The first line 410 with the plurality ofsegmental lines extending in the longitudinal direction of the panel isformed by patterning the gate metal layer. The first line may be eitherin a monolayer or a multilayer.

The gate line (not shown) connected to each pixel area and the gateelectrode 512 of the driving TFT or the pixel TFT is together formed bythe above mentioned process. For example, the gate line and gateelectrode 512 may be formed simultaneously with the first line 410 bypatterning the first metal layer.

Referring to FIG. 6B, after there is placed a first mask having atransparent area TA corresponding to an area except for the data drivingcircuit DCA on the substrate on which the gate line, the gate electrode512 and the first line 410 with the plurality of segmental lines areformed, a first insulating material, for example any one of siliconnitride (SiN_(x)) or silicon oxide (SiO₂), is deposited on thesubstrate, thereby forming the gate insulating layer 514 at an areaexcept for the data driving circuit DCA.

Although the gate insulating layer 514 is described as a monolayer, itmay be formed of a multilayer with two or more layers consisting of thedifferent materials from each other.

After the gate insulating layer 514 is formed, the first contact hole430 exposing an end of the first line 410 is formed by etching a part ofthe gate insulating layer 514 through the above mentioned mask andlithography process.

As shown in FIG. 6B, the mask process used for forming the first contacthole 430 on the gate insulating layer 514 may be further added to thegeneral mask processes of manufacturing the display panel.

A zinc oxide based material as an oxide semiconductor material, forexample IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), ZIO(Zinc Indium Oxide), is deposited or coated on the gate insulating layer514 to form an oxide semiconductor layer and then the oxidesemiconductor layer is patterned by performing a mask process, therebyforming an active layer or semiconductor layer 516 of an island type onthe gate electrode 512 of each TFT.

Such semiconductor layer 516 is not limited to the above mentioned oxidesemiconductor material, but may also be formed of polycrystallinesilicon (poly-Si), pure or impurity-amorphous silicon (a-Si) and thelike.

To form the semiconductor layer 516 using the poly-Si, an amorphoussilicon layer is typically formed on a substrate 510 and crystallized toform a polycrystalline silicon layer which is then patterned. Theamorphous silicon layer may be formed by a chemical vapor depositionmethod or a physical vapor deposition method. When (or after) theamorphous silicon layer is formed, it may be dehydrogenated to reducehydrogen concentration. One of solid phase crystallization (SPC), rapidthermal annealing (RTA), metal induced crystallization (MIC), metalinduced lateral crystallization (MILC), a super grain silicon (SGS)process, excimer laser annealing (ELA), and sequential lateralsolidification (SLS) may be used to crystallize the amorphous siliconlayer.

Next, an ohmic contact layer 518 is formed on the semiconductor layer516 and a source/drain electrode 520 is formed thereon. During theforming process of the source/drain electrode 520, there issimultaneously formed the second line 420, which electrically connectstwo first segmental lines of the first line 410 adjacent to each othervia the first contact hole 430 previously formed in the signal linearea.

In more detail, after the semiconductor layer 516 and/or the ohmiccontact layer 518 is formed, a second metal layer is formed on thesubstrate by depositing a metallic material or a metal alloy for thesource/drain such as one or more of Cu, Cr, Al, AlNd, Ti, Ta, Mo, MoTi,Mo alloy and the like on the entire surface of the substrate. The secondline 420 is formed in the signal line area by patterning the secondmetal layer by performing a mask and lithography process.

The data line (not shown) connected to each pixel area and thesource/drain electrode 520 of the driving TFT or the pixel TFT istogether formed by the above mentioned process. For example, the dataline and the source/drain electrode 520 may be formed simultaneouslywith the second line 420 by patterning the second metal layer.

An etch stopper in an island shape consisting of an inorganic insulatingmaterial may be formed instead of or in addition to the ohmic contactlayer 518 and the source/drain electrode in contact with the top surfaceof both ends of the semiconductor layer by patterning the source/drainmetal layer.

The patterning process of the semiconductor layer and source/drain mayuse one of a half-tone mask, a slit mask and the like havingsemitransparent property at some area, which forms a photoresist layerhaving three kinds of thickness as a single mask so as to perform thepatterning of two layers by only a single mask.

Although not shown, after the source/drain patterning is formed, acontact hole may be formed by forming a passivation layer and thenremoving a part of the passivation layer on the drain electrode, and apixel electrode may be formed to be connected to the drain electrode viathe contact hole. At this time the pixel electrode may be a transparentelectrode. Material for the transparent, electrode may be a metal oxidesuch as ITO (Indium Tin. Oxide), IZO (In₂O₃ZnO) and IZTO (In₂O₃ZnOSnO),or a combination of metal and oxide (e.g. an oxide doped with a metal)such as ZnO:Al or SnO₂:Sb, but it is not limited thereto.

The signal line is not formed of a single line extended over the entirepanel in the longitudinal direction of the panel but the plurality ofsegmental lines with the gate metal when the array substrate ismanufactured in FIGS. 6A through 6C. Since the following processesproceed in this state, the plurality of segmental lines continue to bedisconnected until the end of the source/drain metal patterning processas shown in FIG. 6C. Therefore although static electricity is generatedfrom the equipment in the following processes, the segmental lines beingdisconnected may not conduct the static electricity, thereby preventingthe damage from the above mentioned static electricity in variouspatterning processes.

The first embodiment in FIGS. 4, 5 and 6A through 6C has the effect thatthe electrical conductivity of the signal line is excellent since thewhole signal line comprises a plurality of segmental lines of the firstline 410 and the second line 420 as a connection line made oflow-resistance metal, wherein one additional mask process may be used inorder to form the first contact hole 430 on the gate insulating layer514.

The above embodiment is not limited to the structure of the thin filmtransistor as shown in FIGS. 4, 5 and 6A through 6C. If the Signal lineincludes the first line with the plurality of segmental lines and thesecond line at the different layer from the first line whichelectrically connects the segmental lines, the above embodiment may beapplied to the array substrate on which any structure of the thin filmtransistor is formed.

FIGS. 7 and 8A through 8D illustrate the configuration of the secondembodiment. FIG. 7 is a cross-sectional view of a part of a signal lineon the array substrate according to the second embodiment. FIGS. 8Athrough 8D are cross-sectional views showing manufacturing processes ofthe array substrate according to the second embodiment.

The second embodiment is similar to the first embodiment. While thesecond line 420 of FIGS. 4, 5, 6A through 6C is formed of thesource/drain pattern in the first embodiment, the second line 720 isformed of a pixel electrode material in the second embodiment. Thesecond embodiment is also different from the first embodiment in that asecond contact hole 730 for connecting the second line and the firstline is formed through a gate insulating layer 514 and a passivationlayer 522.

FIG. 7 illustrates a cross-sectional view of a signal line of the arraysubstrate on a left side, and a thin film transistor on a right side,according to the second embodiment.

In more detail, the second embodiment relates to the signal line,specifically forward/backward start signal line, extending in parallelwith the data line in the non-active area of the array substrate withGIP structure. As shown in FIG. 7, such signal line may include a firstline 410 with a plurality of segmental lines and a second line 720 as aconnecting line. The first line 410 is formed of the gate metal layerand is segmented into a plurality of segmental lines extending in thelongitudinal direction of the panel or the array substrate in order tobe disconnected (in other words, a gap may be formed in each casebetween two neighboring segmental lines). The second line 720 may beformed of a pixel electrode metal at the different layer from the firstline 410, and electrically connects ends of two segmental lines of thefirst line 410 adjacent to each other. The gate insulating layer 514 anda passivation layer 522 may be formed between the layers of the firstline 410 and second line 720.

The second line 720 may be connected with the first line 410 via asecond contact hole 730 which is formed through the gate insulatinglayer 514 and the passivation layer 522 on the top portion of the firstline 410 to expose a part of the first line 410.

Each layer of the thin film transistor shown in the right side of FIG. 7is illustrated to understand the material and the process for formingthe signal line of the array substrate according to the secondembodiment.

FIGS. 8A to 8D are cross-sectional views showing manufacturing processesof the array substrate according to the second embodiment.

The manufacturing processes of the array substrate according to thesecond embodiment are similar to some of manufacturing processes of thearray substrate according to the first embodiment, therefore detaileddescription of these manufacturing processes are omitted for the sake ofbrevity.

Referring to FIG. 8A, the first metal layer is formed on a transparentinsulation substrate such as a glass or a plastic substrate bydepositing a metallic material or a metal alloy for the gate ofrelatively low specific resistance such as one or more of Al, AlNd, Cu,Mo, MoTi and the like on the entire surface of the substrate. The gateline (not shown) connected to each pixel area and the gate electrode 512of the driving TFT or the pixel TFT are simultaneously formed by theabove mentioned process.

A first insulating layer is formed of an inorganic insulating material,and is formed on the substrate on which (i) the gate line, (ii) the gateelectrode 512 and (iii) the first line 410 with the plurality ofsegmental lines are formed.

Next, the semiconductor layer 516, an ohmic contact layer 518 and asource/drain electrode 520 for a thin film transistor in the pixel areaand the driving circuit area are sequentially formed. These processesare described in the first embodiment in FIG. 6 so that the duplicatedescription is omitted.

Referring to FIG. 8B, after the forming process of the source/drainelectrode 520, the passivation layer 522 is formed thereon.

Referring to FIG. 8C, a drain contact hole through the passivation layer522 may be formed to expose a part of the drain electrode of the thinfilm transistor to connect the pixel electrode. During the formingprocess of the drain contact hole, the second contact hole 730 exposingan end of the first line 410 is formed by etching a part of the gateinsulating layer 514 and the passivation layer 522 through the mask andlithography processes.

Referring to FIG. 8D, during the forming process of the pixel electrode,the second line 720 is formed which connects the segmental linesadjacent to each other via the second contact hole 730. The second line720 is formed of the same material as the pixel electrode 526. Thesecond line 720 may be made of a transparent conducting material withrelatively large work function such as a metal oxide such as ITO (IndiumTin Oxide), IZO (In₂O₃ZnO) and IZTO (In₂O₃ZnOSnO), or a combination ofmetal and oxide (e.g. an oxide doped with a metal) such as ZnO:Ai orSnO₂:Sb, but it is not limited thereto.

Compared to the first embodiment in FIGS. 4, 5 and 6A through 6C, in thesecond embodiment the material and the layer of the second line 720 toconnect the segmental lines of the first line 410 as a jumper aredifferent from that of the first line 410. In the second embodiment, thesecond contact hole 730 and the second line 720 are simultaneouslyformed by the process for forming the contact hole 524 and the pixelelectrode 526 in the pixel area, without the additional mask processnecessary for forming the first contact hole 430 through the gateinsulating layer 514 as in the first embodiment. While the second line420 as the jump-connecting line in the first embodiment is formed of thesource/drain metal with the excellent electrical conductivity, thesecond line 720 in the second embodiment is formed of the transparentconducting material such as the pixel electrode material so that theymay have the different conductive properties from each other.

The signal line is not formed of a single line extended over the entirepanel in the longitudinal direction of the panel but is formed of theplurality of segmental lines with the gate metal when the arraysubstrate is manufactured as in FIG. 8A. Because the following processesproceed, in this state, the plurality of segmental lines remaindisconnected (in other words, gaps remain between neighboring segmentallines; in still other words, neighboring segmental lines are notelectrically connected to one another) until the end of the pixelelectrode forming process as shown in FIG. 8D. Therefore, although thestatic electricity is generated from the equipment in the followingprocesses, due to the segmental lines being disconnected the staticelectricity is not conducted, thereby preventing the damage from theabove mentioned static electricity in various patterning processes.

FIGS. 9, 10, and 11A through 11D illustrate the configuration of thethird embodiment. FIG. 9 is a top plan view of a part of a signal lineon the array substrate according to the third embodiment. FIG. 10 is across-sectional view of a part of a signal line on the array substrateaccording to the third embodiment. FIGS. 11A through 11D arecross-sectional views showing a manufacturing process of the arraysubstrate according to the third embodiment.

The third embodiment relates to the Signal line, specificallyforward/backward start signal line, extending in parallel with the dataline in the non-active area to transfer a signal to the gate drivingcircuit. As shown in FIG. 9, such signal line may include a first line910 with a plurality of segmental lines, a third line 920 and a fourthline 930. The first line 910 is formed of the gate metal layer and issegmented into a plurality of segmental lines extending in thelongitudinal direction of the panel or the array substrate in order tobe disconnected. The third line 920 may be formed of a source/drainmetal at a different layer than the first line 910 and partiallyoverlapped with two segmental lines of the first line 910. The fourthline 930 is formed of a different material and formed at a differentlayer than the first line 910 and the third line 920 and electricallyconnects the two segmental lines of the first line 910 to the third line920. In the third embodiment, the first line 910 is formed of a gatemetal and the third line 920 is formed of a source/drain metal, and thefourth line 930 is formed of a pixel electrode material. The fourth line930 is also connected to both the first line 910 and the third line 920via a third contact hole 940 formed through a gate insulating layer anda passivation layer to expose a part of the first line 910 and a fourthcontact hole 950 formed through the passivation layer to expose a partof the third line 920.

In the second embodiment the third line 920 of the source/drain metallayer is formed at a different layer than the first line 910 and theyare connected with each other through the fourth line 930.

FIG. 10 illustrates a cross-sectional view of a part of a signal linetaken along II-II′ line of FIG. 9 on the array substrate on a left side,and a thin film transistor on a right side, according to the thirdembodiment.

As shown on the left side of FIG. 10, the signal line according to thethird embodiment may include the first line 910 with a plurality ofsegmental lines, a third line 920 as a connecting line and a fourth line930. The first line 910 with the plurality of segmental lines is formedof the same metal and process as the gate electrode 1012 of the thinfilm transistor. The third line 920 may be formed of the same metal andprocess as the source/drain electrode 1020 of the thin film transistorand disposed between two segmental lines of the first line 910 adjacentto each other. The forth line 930 is formed of a different material andat a different layer than the first line 910, namely the pixel electrodelayer, and the third line 920 and electrically connects the twosegmental lines of the first line 910 to the third line 920.

The fourth line 930 also connects both the first line 910 and the thirdline 920 via a third contact hole 940 formed through the gate insulatinglayer 1014 and the passivation layer 1022 coated on the first line 910to expose a part of the first line 910, and via a fourth contact hole950 formed through a part of the passivation layer 1022 on the thirdline 920 to expose a part of the third line 920. Pixel electrode 1026may be electrically connected to drain electrode 1020 through contacthole 1024.

FIGS. 11A through 11D are cross-sectional views showing manufacturingprocesses of the array substrate according to the third embodiment.

Referring to FIG. 11A, the first metal layer is formed on a transparentinsulation substrate 1010 such as a glass or a plastic substrate bydepositing a metallic material or a metal alloy for the gate ofrelatively low specific resistance such as one or more of Al, AlNd, Cu,Mo, MoTi and the like on the entire surface of the substrate.

The gate line (not shown) connected to each pixel area and the gateelectrode 1012 of the driving TFT or the pixel TFT are simultaneouslyformed by the above mentioned process.

A first insulating layer 1014 is formed of an insulating material on thesubstrate on which the gate line, the gate electrode 1012 and the firstline 910 with the plurality of segmental lines are formed.

Referring to FIG. 11B, the semiconductor layer 1016 is formed in a thinfilm transistor area on the gate insulating layer 1014 in the shape ofan island and an ohmic contact layer 1018 is formed on the semiconductorlayer 1016, and during a source/drain electrode 1020 is formed thereon,the third line 920 is formed of a source/drain metal between thesegmental lines of the first line 910 in the signal line area.

In this time the third line 920 may be formed to be partially overlappedwith two segmental lines of the first line 910. For example, a part ofthe third line 920 is formed above a part of a segmental line of thefirst line 910, and another part of the third line 920 is formed above apart of another segmental line of the first line 910.

The forming process of the semiconductor layer 1016 and an ohmic contactlayer 1018, and an etch stopper instead of the ohmic contact layer 1018correspond to those of the first embodiment, therefore the detaileddescription thereof is omitted herein for the sake of brevity.

Referring to FIG. 11C, the passivation layer 1022 is coated on an entiresurface of the substrate on which the source/drain electrode 1020 isformed in the thin film transistor area and the third line 920 in thesignal line area, and a drain contact hole through the passivation layer1022 may be formed to expose a part of the drain electrode of the thinfilm transistor to connect the pixel electrode. During the formingprocess of the drain contact hole, the third contact hole 940 exposingan end of the first line 910 is formed by etching a part of the gateinsulating layer 1014 and the passivation layer 1022 at ends of thefirst line 910 through the mask and lithography processes. The fourthcontact hole 950 is simultaneously formed by etching a part of thepassivation layer 1022 on the first line 910.

Referring to FIG. 11D, during the forming process of the pixel electrode1026, there is formed the fourth line 930 which connects the segmentallines adjacent to each other via the third and fourth contact holes 940,950. The fourth line 930 is formed of the same material as the pixelelectrode. The fourth line 930 may be made of a transparent conductingmaterial with relatively large work function such as a metal oxide suchas ITO (Indium Tin Oxide), IZO (In₂O₃ZnO) and IZTO (In₂O₃ZnOSnO), acombination of metal and oxide (e.g. an oxide doped with a metal) suchas ZnO:Al or SnO₂:Sb, but it is not limited thereto.

The signal line is not formed of a single line extended over the entirepanel in the longitudinal direction of the panel but of the plurality ofsegmental lines with the gate metal when the array substrate of thethird embodiment is manufactured. Since the following processes proceedin this state, the plurality of segmental lines remains disconnecteduntil the end of the pixel electrode forming process as shown in 11D.Therefore although the static electricity is generated from theequipment in the following processes, because the segmental lines aredisconnected, the static electricity is not conducted, therebypreventing the damage from the above mentioned static electricity invarious patterning processes.

In the third embodiment, an additional mask process is not necessary forforming the first line, the third line, the fourth line, the thirdcontact hole and the fourth contact hole except for the general maskprocesses used for the manufacturing method of the conventional arraysubstrate. Namely, the first line with the segmental lines issimultaneously formed in the patterning process of the gate metal layer,the third line is simultaneously formed in the patterning process of thesource/drain metal layer, the third and the fourth contact holes aresimultaneously formed in the forming process of the contact hole forconnecting between the drain electrode and the pixel electrode, and thefourth line is simultaneously formed in the patterning process of thepixel electrode.

The first line as the main signal line and the third line 920 as thejump-connecting line are formed of the gate or the source drain metalwith the low resistance in the third embodiment in FIGS. 9, 10 and 11Athrough 11D. As a result, the conductive property of the entire signalline is excellent. In addition, an additional mask process is notimplemented according to the third embodiment, in contrast to themanufacturing method of the conventional array substrate.

As mentioned above, various embodiments may prevent the generation ofstatic electricity from the elongated signal line during manufacturingthe display panel with the GIP structure so that they may prevent thelarge static electricity from destroying the gate metal and the like.

In more detail, in the array substrate with the GIP structure, thesignal line elongated from the non-active area to transfer varioussignals to the driving circuit area is formed to be divided into thefirst line with the plurality of segmental lines and the second tofourth lines as a jumper. Hence, damage to the substrate due to thegenerated static electricity in the following patterning processes maybe eschewed.

Although various embodiments have been described up to now withreference to the accompanying drawings, the present invention is notlimited to them.

In addition, since terms, such as “including,” “comprising,” and“having” mean that one or more corresponding components may exist unlessthey are specifically described to the contrary, it shall be construedthat one or more other components can be included. All the terms thatare technical, scientific or otherwise agree with the meanings asunderstood by a person skilled in the art unless defined to thecontrary. A term ordinarily used like that defined by a dictionary shallbe construed that it has a meaning equal to that in the context of arelated description, and shall not be construed in an ideal orexcessively formal meaning unless it is clearly defined in the presentspecification.

Although the embodiments of the present invention have been describedfor illustrative purposes, those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention. Therefore, theembodiments disclosed in the present invention are intended toillustrate the scope of the technical idea of the present invention, andthe scope of the present invention is not limited by the embodiment. Thescope of the present invention shall be construed on the basis of theaccompanying claims in such a manner that all of the technical ideasincluded within the scope equivalent to the claims belong to the presentinvention.

What is claimed is:
 1. An array substrate comprising: an active area(AA) including a plurality of pixels defined at an intersection area ofa gate line (110) and a data line; a gate driving circuit (GCA) formedat one side of a non-active area (NA); and a signal line extending inparallel with the data line in the non-active area (NA) to transfer asignal to the gate driving circuit (GCA), the signal line including afirst line with a plurality of segmental lines, and at least oneadditional line formed of a different material and formed at a differentlayer than the first line, the at least one additional line electricallyconnecting two segmental lines of the first line adjacent to each other.2. The array substrate of claim 1, wherein the at least one additionalline comprises a second line, wherein the first line is formed of a gatemetal and the second line is formed of a source/drain metal, and thesecond line is connected with the first line via contact hole formedthrough a gate insulating layer.
 3. The array substrate of claim 1,wherein the at least one additional line comprises a second line whereinthe first line is formed of a gate metal and the second line is formedof a pixel electrode material, and the second line is connected with thefirst line via a contact hole formed through a gate insulating layer anda passivation layer.
 4. The array substrate of claim 1, wherein the atleast one additional line comprises a third line formed of a differentlayer than the first line and partially overlapped with two segmentallines of the first line adjacent to each other, and a fourth lineelectrically connecting the two segmental lines of the first line to thethird line.
 5. The array substrate of claim 4, wherein the first line isformed of a gate metal and the third line is formed of a source/drainmetal, the fourth line is formed of a pixel electrode material, andwherein the fourth line is connected to both the first line and thethird line via a contact hole formed through gate insulating layer and apassivation layer to expose a part of the first line and an additionalcontact hole formed through the passivation layer to expose a part ofthe third line.
 6. The array substrate of claim 1, wherein the signalline is a forward start signal line or a backward start signal linesupplying a start pulse to the gate driving circuit (GCA) and disposedbetween the gate driving circuit (GCA) and the active area (AA).
 7. Amethod of fabricating an array substrate, the method comprising: forminga first line with a plurality of segmental lines as a part of a signalline in a non-active area (NA) by patterning a first metal layer on asubstrate; forming one or more insulating layers on the substrate onwhich a gate is patterned; forming at least one contact hole through theone or more insulating layers to expose a part of the first line; andforming at least one additional line by patterning a second metal layerdifferent from the first metal layer to electrically connect twosegmental lines of the first line adjacent to each other.
 8. The methodof claim 7, wherein the first metal layer is a gate metal layer, the oneor more insulating layers include gate insulating layer and the secondmetal layer is a source/drain metal layer.
 9. The method of claim 7,wherein the first metal layer is a gate metal layer, the one or moreinsulating layers include a gate insulating layer and a passivationlayer, and the second metal layer is a pixel electrode layer.
 10. Themethod of claim 7, wherein the first metal layer is a gate metal layer,the one or more insulating layers include a gate insulating layer and atleast one passivation layer, wherein forming the one or more insulationlayers, the at least one contact hole and the at least one additionalline includes: forming (i) the gate insulating layer on the substrate onwhich the gate is patterned, and (ii) a third line with a source/drainmetal, wherein ends of the third line are partially overlapped with thetwo segmental lines of the first line adjacent to each other; forming(i) the passivation layer on the non-active area (NA), (ii) a contacthole penetrating the gate insulating layer and the passivation layer toexpose a part of the first line, and (iii) an additional contact holepenetrating the passivation layer to expose a part of the third line;and forming a fourth line electrically connecting the two segmentallines adjacent to each other to the third line through (i) the contacthole penetrating the gate insulating layer and the passivation layer,and (ii) the additional contact hole penetrating the passivation layerduring a pixel electrode patterning process.
 11. The method of claim 7,wherein the signal line is a forward start signal line or a backwardstart signal line supplying a start pulse to the gate driving circuit(GCA) and disposed between the gate driving circuit (GCA) and an activearea (AA).